Various semiconductor devices used in various applications and which serve a variety of functions, employ SRAM cells or other repeating device cells that are arranged in arrays and coupled to one another. As one example, word line decoder devices serve a variety of functions in the electronics world, and utilize a high number of word line decoder cells and SRAM (static random access memory) cells. These semiconductor devices typically include layouts that utilize repeating arrays for design convenience. One common layout includes repeating arrays of the word line decoder cells. Such an arrangement of repeating cells is favored because it represents an established and common design that provides high levels of integration and includes multiple functional transistors in minimal area. One common arrangement includes word line decoder cells disposed in repeating arrays that include longitudinal word line decoder cells laid end-to-end along bit lines.
Word line decoder cells may include multiple levels of metal interconnect layers with the upper metal layer often used as word line connectors and one of the subjacent, intermediate metal layers used for power signals, ground signals or other signals and/or other interconnection functions. Because there is a challenge to always increase integration levels by producing smaller features, one method and technique for forming such word line decoder cells includes using DPL (double patterning lithography) to form a pattern in a metal interconnect layer. DPL involves the use of two photomasks, two sets of photolithography operations and two etching operations to form one pattern in the layer being patterned. An advantage of this DPL technique is that patterns with smaller pitches can be created. When a metal interconnect layer is formed to very small feature sizes, it can perform various interconnection functions. According to known technology, the upper metal layer may be used for global signal routing and large size devices and is also utilized for poly gate stitch routing.
Transistors formed in the word line decoder cells have polysilicon gates and stitching may be used to couple transistors that are spaced apart by a significant distance. This applies advantageously to longitudinally spaced transistors. Word line decoder cells are often formed in repeating arrays that include longitudinal word line decoder cells laid end-to-end along bit lines. The polysilicon gate transistors formed in one word line decoder cell are coupled, often by a polysilicon lead extending longitudinally from cell to cell, to transistors in other cells. Since polysilicon is a semiconductor material and not a conductive material such as metal, the polysilicon gates include some level of resistance and when the polysilicon leads extend over a significant distance from cell to cell coupling transistors, the aggregate resistance is significant and can cause signal delays, in particular signal RC delays. For this reason, the upper metal layer which is a conductive material, may be used to couple polysilicon transistor gates from one word line decoder cell to further transistor polysilicon gates in other word line decoder cells.
While the use of DPL enables a tighter pitch to be produced in underlying metal patterns which enables the upper metal layer pattern to extend through void areas in the underlying metal pattern for poly gate stitch routing, the double pattern lithography operations carry with them inherent shortcomings. One shortcoming associated with the use of double patterning lithography is high cost as two photomasks must be fabricated and used. Further, the two photomasks that combine to form one pattern are produced by a mask decomposition method which can be unreliable and time consuming. In addition to the costs associated with carrying out two each of the photolithography operations of coating, exposing and developing, and two etching and stripping operations, the time associated with having to perform each of these operations two times carries with it a cost and delay in cycle time. Finally, the use of yet another photomask carries with it an additional inherent risk of misalignment and/or rework.
Conventional operations for forming devices with repeating word line decoder cells, SRAM cells, or other cells, using DPL methods, therefore include various shortcomings.